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Test Engineer Salary in Palo Alto, CA
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Software Engineer (379555)
Placement Services USA, Inc., Palo Alto, CA, US
Will test, debug, and verify in-house chip design as a member of the verification team; create the Universal Verification Methodology (UVM) testbench that is written in System Verilog to verify the functionality and performance of the chip; examine the interrupt, register access, and Direct Memory Access (DMA) functionality in a full chip simulation with Praveen; verify the detailed feature of a device link controller module with team members; collaborate across company's verification teams to bring up new verification methods and test plans; engage in design-verification cross-team reviews to come out better solution for the hardware bug.A Master's degree in Electrical Engineering or Electrical Engineering and Computer Science, or Electrical and Computer Engineering, or Computer Engineering, or a related field is required.Please copy and paste your resume in the email body do not send attachments, we cannot open them and email them at candidates at placementservicesusa.com with reference #379555 in the subject line.Thank you.